As device speeds and device integration increase, signal delays may also be increased, for example, due to parasitic capacitance introduced by interconnection structures. Advances in integration technology have led to the development of three-dimensional integration, where wafers may be stacked three-dimensionally, in contrast to the conventional two-dimensional approach. In a three-dimensional wafer stack package (WSP), a technique called through-silicon via (TSV) can be used to extend the via hole through a substrate so that a conductive via may be formed to vertically extend and completely penetrate through the substrate. Such a TSV structure may provide higher speeds, higher integration, and improved functionality in comparison to a long wire pattern interconnection. Multiple substrates including TSVs can be stacked on one another to achieve three-dimensional integration. In particular, the TSVs of different substrates can conduct signals from one substrate to another without the use of, for example, wires. Three-dimensional integration is usually performed after device passivation.
A TSV structure may be formed by forming an opening or hole in a substrate, such as a silicon substrate. An insulation layer, such as silicon dioxide (SiO2), may be formed on the substrate and in the opening, and a barrier or seed layer, such as titanium nitride (TiN), may be formed on the insulation layer. A conductive metal layer, such as a copper layer (Cu), may be formed in the opening, for example, by a plating process or deposition process. A support attachment may also be formed on the conductive metal layer extending along the surface of the substrate. A backside of the substrate may then be recessed to expose at least a portion of the conductive metal layer, thereby forming a conductive via extending through the substrate. The substrate may then be diced, stacked on other substrates, and molded to provide a three-dimensional wafer stack package.
Two approaches that can be used in the formation of TSV structures include a “via first” approach, and a “via last” approach. According to the via first approach, TSVs may be formed through the substrate before back end processing. Subsequently, the substrate can be thinned and bound together with other substrates to provide a three dimensional stack structure. Alternatively, according to the via last approach, the via can be formed through the substrate after the backend processing or after a bonding process. TSV structures are also discussed in, for example, Korean Patent Application No. 10-2005-060741, U.S. Patent Application Publication No. 2008/0017968, and U.S. Pat. No. 6,501,176.